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The ChibiOS/RT kernel has been ported to a variety of different architectures and compilers in order to ensure portability however our current strategy is to support a reduced number of specific MCUs with a complete HAL.
The rationale is that we prefer to offer excellent support for few popular families rather than some kind of support for as many families as possible. Numerous unofficial ports are not included in the main distribution but are maintained by the respective authors.
The following list includes the architectures supported by ChibiOS/RT out of the box. The following ports are thoroughly tested before each stable release. For each architecture a list of explicitly supported micro controller families (drivers, demos) is specified.
|Core Architecture||Compiler||Supported Platforms|
|ARM Cortex-M0 (ARMv6-M)||GCC||LPC11xx, LPC11Uxx, STM32F0xx|
|ARM Cortex-M0 (ARMv6-M)||RVCT||LPC11xx, LPC11Uxx, STM32F0xx|
|ARM Cortex-M3 (ARMv7-M)||GCC||LPC13xx, STM32F1xx, STM32F2xx, STM32L1xx|
|ARM Cortex-M3 (ARMv7-M)||IAR||LPC13xx, STM32F1xx, STM32F2xx, STM32L1xx|
|ARM Cortex-M3 (ARMv7-M)||RVCT||LPC13xx, STM32F1xx, STM32F2xx, STM32L1xx|
|ARM Cortex-M4 (ARMv7-ME)||GCC||STM32F3xx, STM32F4xx|
|ARM Cortex-M4 (ARMv7-ME)||IAR||STM32F3xx, STM32F4xx|
|ARM Cortex-M4 (ARMv7-ME)||RVCT||STM32F3xx, STM32F4xx|
|MegaAVR||GCC||ATmega128, AT90CAN128, ATmega328p, ATmega1280|
|Power Architecture e200z||GCC/HighTec||SPC56x (all)|
See the Features Matrix page to verify the device drivers support status for each of the above platforms or the Performance Data section to discover how ChibiOS/RT performs on the above core architectures.
In this section are included those ports contributed by various developers and not yet migrated into the official list. The reason is usually that I am unable to perform the pre-release tests because lack of hardware. The contributed ports are only available from the repository under ./branches or from the author directly. No support is provided for the ports in this list, please contact the authors.
It is possible that the above ports will be integrated into the mainline at some point.