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ChibiOS notes for Cortex-M architecture

Integrating an RTOS is usually not a trivial task, much of the complexity is hidden in ChibiOS because the whole environment is provided already integrated with startup files, build environment and HAL.

Problems start when the RTOS is used “naked” and integrated in a different infrastructure. There are details to be considered.

This article applies to both RT and NIL.

Startup Requirements

The startup files provided with ChibiOS already implement everything is required for correct functionality. The easiest approach is to use the startup files and build environment provided in ChibiOS. Should this not be possible then the following requirements must be fulfilled:

  • Startup files are responsible for allocating and initializing both the Cortex-M Process and Main Stacks.
  • Stacks must be aligned to a 32 bytes boundary.
  • Startup files are responsible for initializing the CONTROL register in dual stack and privileged modes.
  • Startup files are responsible for VTOR register initialization (not applicable to M0 cores).
  • The main() function must be entered with interrupts disabled (cpsid i).

The above steps must be performed before entering the main() function.

Additional FPU Requirements

When using a device with FPU and kernel port option CORTEX_USE_FPU is enabled then the following requirements must be fulfilled.

  • Startup files are responsible for initializing SCB FPCCR with ASPEN and LSPEN bits enabled.
  • SCB CPACR must be set to 0x00F00000.
  • FPU FPSCR register must be cleared.
  • SCB FPDSCR must be cleared.
  • CONTROL register must have the FPCA bit enabled.

The above steps must be performed before entering the main() function.

Expected Symbols

If the core allocator is used and the CH_CFG_MEMCORE_SIZE option is set to zero then the linker scatter files must export two symbols:

  • __heap_base__ represents the start of unused RAM area.
  • __heap_end__ represents the end (+1) of unused RAM area.

The unused RAM is used as heap space for the allocator.

MPU usage notes

The option PORT_ENABLE_GUARD_PAGES enables stack guard pages using the MPU, the following requirements must be fulfilled.

  • MPU region zero is reserved for the RTOS, must not be touched by user code. Other regions may be used.

Interrupts Management

The RTOS makes several assumptions regarding interrupts. The following requirements must be fulfilled.

  • Priority grouping must not be used. If grouping is required then the port layer must be reconfigured carefully.
  • Priorities 0, 1 and 2 (highest ones) are reserved as fast interrupts. ISRs at those priorities must not use any RTOS functionality. Use of the CH_IRQ_HANDLER(), CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() is forbidden.
  • Fast ISRs can be declared using the specific CH_FAST_IRQ_HANDLER() macro but it is not mandatory.
  • Normal ISRs must be declared using the CH_IRQ_HANDLER() macro and must include the CH_IRQ_PROLOGUE() and CH_IRQ_EPILOGUE() macros at very beginning and very end of the ISR function.
  • If, for whatever reason, an ISR is declared without using the appropriate macros then it must have a priority higher than any RTOS-compliant ISR and must not use any RTOS functionality.

Failure to implement the above requirements shall result in hard to debug, sporadic and very subtle problems, make sure to understand and implement correctly.

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