Priority is an important concept when using a RTOS, ChibiOS/RT is no different in this regard.
Priorities in ChibiOS/RT are a contiguous integer range starting from
LOWPRIO up to
main() thread is started at the
NORMALPRIO priority level which is in the middle of the allowable range.
When designing your application you should never think in terms of absolute priorities because the numeric range may change in future versions, much better reason in terms of relative priorities from the above symbolic levels, for example
NORMALPRIO-1, this is guaranteed to be portable.
The following priority levels are defined:
|zero||Reserved priority level, all the possible priority levels are guaranteed to be greater than zero.|
| ||Special priority level reserved for the Idle Thread.|
| ||Lowest priority level usable by user threads.|
| ||Central priority level, the
| ||Highest priority level usable by user threads. Above this level the priorities are reserved.|
| ||Absolute priority level, highest reserved priority level. Above this levels there are the hardware priority levels used by interrupt sources.|
The rule is very simple, among all the threads ready for execution, the one with the highest priority is the one being executed, no exceptions to this rule.
Priorities are not related to CPU use percentages, a thread at level
NORMALPRIO+40 is perfectly equivalent to a thread at
NORMALPRIO+5 if in between there are no other threads. Remember, the absolute values have no meaning, only the relative priorities among all the existing threads are important.
Unlike many other RTOSs, ChibiOS/RT allows for multiple threads at the same priority level, such threads are rotated using a Round Robin algorithm.
In ChibiOS/RT you should consider interrupts as special tasks having a priority range allocated above the priority range reserved for normal threads. The base rule still applies, the highest priority task/thread is the one being executed. This is especially true in those architectures, like the Cortex-Mx for example, that allow the preemption of interrupt handlers.